# time sensitive question

[30 pts] Problem 1

• Write a Verilog code that models this design in combinational logic. Assume a and b are 5-bit signed (1bit sign, 3 bit integer,1 bit fraction) numbers and C is 7-bit signed (1bit sign, 5 bit integer,1 bit fraction) number. This will be all combinational logic.
• How many bits does Sum1, Sum2 and avg need? Say in bits (sign, integer,fraction) for each one.
• Modify the block diagram and add Pipeline registers for the inputs, outputs and in the middle stages.
• Modify your Verilog codes to model this pipelined architecture in your design.
• Explain and draw a line where is the critical path in the original design (a) and pipeline design (c)?

[30pts] Problem3: Encoder Decoder, Memory and State machine

Using Hamming code described in class, design an error correction code (ECC) for a 8-bit data word.

Reminder:

– Required number of check bits is log2N+1, where N is data word length

– ECC bits whose indices are powers of two are used as check bits.

– If we write the indices of ECC bits in binary, the check bit with a 1 in position i of its index is the XOR of data ECC bits that have a one in position i of their indices.

[3 pts] What is the length of total code word? Which bits are check bits and which one are data bits?

[7 pts] Write down the equations and computation of the ECC bits for 8-bit data 01111111 and write the complete Encoded code word. This needs to show your work.

Now You need to design a complete Verilog for this Encoder Decoder, Memory and State machine shown below. Memory module has 128x8bit data prestored. Upon start signal and Enc=1 Encoder reads inputs from memory, performs encoding and sends out the Encoded output to store in the output SSRAM. When all 128 data are encoded. When Enc=0, the data from the output SSRAM is read by Decoder module and finds out if there is an error (Error=1 or 0), the Error Location, Decoded Out (the corrected data).

[2 pt] What is the size of both SSRAMs? Address bit, data bits and total size.

[5 pt] Draw a detailed block diagram of the module with inputs to each block, required signals and their connections. Explain how your module works.

[5 pts] Write verilog for writing and reading from your two memories (based on the signals that you defined).

[12 pt] Design a state machine that computes the function

• [3 pts] How many states are required?
• [2 pts] Draw state diagram for the state machine
• [7 pts] Write the verilog for the state machine (both state logic and state transition)

[6 pts] Write Verilog for the datapath and complete module.

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